STE100A View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STE100A' PDF : 82 Pages View PDF
STE10/100A
Registers and descriptors description
Table 8. Control/status register description (continued)
Bit #
Name
Description
Jabber clock
2
JCLK
0: cut off transmission after 2.6 ms (100Mbps) or
26 ms (10Mbps).
1: cut off transmission after 2560 byte-time.
Non-Jabber
0: if jabber expires, re-enable transmit function
1
NJ after 42 ms (100Mbps) or 420ms (10Mbps).
1: immediately re-enable the transmit function
after jabber expires.
Jabber disable
0
JBD
1: disable transmit jabber function
CSR16 (offset = 80h), ACSR5 - Assistant CSR5 (Status register 2)
31
30
29
28
27
26
25~ 23
TEIS
REIS
XIS
TDIS
---
PFR
BET
Transmit early interrupt status
Transmit early interrupt status is set to 1 when
TEIE (bit 31 of CSR17 set) is enabled and the
transmitted packet is moved from descriptors to
the TX-FIFO buffer. This bit is cleared by writing
a 1.
Receive early interrupt status.
Receive early interrupt status is set to 1 when
REIE (CSR17 bit 30) is enabled and the
received packet has filled up its first receive
descriptor. This bit is cleared by writing a 1.
Transceiver (XCVR) interrupt status. Formed by
the logical OR of XR8 bits 6~0.
Transmit deferred interrupt status.
Reserved
PAUSE frame received interrupt status.
1: indicates receipt of a PAUSE frame while the
PAUSE function is enabled.
Bus error type. This field is valid only when FBE
(CSR5 bit 13, fatal bus error) is set. There is no
interrupt generated by this field.
000: parity error, 001: master abort, 010:
target abort.
011, 1xx: reserved
Default
0
0
1
0
0
000
RW type
RO/LH*
RO/LH*
RO/LH*
RO/LH*
RO/LH*
RO
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