STE100A View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STE100A' PDF : 82 Pages View PDF
STE10/100A
Registers and descriptors description
Table 14.
Bit#
29
28,27
26
25
24
23
22
21-11
10-0
TDES2
31~0
TDES3
31~0
Transmit descriptor description (continued)
Name
Description
FS First descriptor
--- Reserved
AC
TER
Disable add CRC function
End of ring
TCH
DPD
2nd address chain. Indicates that the buffer 2 address is the next descriptor
address
Disable padding function
--- Reserved
TBS2 Buffer 2 size
TBS1 Buffer 1 size
BA1
Buffer address 1. No alignment limitations imposed on the transmission
buffer address.
BA2
Buffer address 2. No alignment limitations imposed on the transmission
buffer address.
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