STI5107 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STI5107' PDF : 14 Pages View PDF
Architecture features
STi5107
2.11
Internal peripherals
The STi5107 has many dedicated internal peripherals for digital TV receiver applications,
including:
● one smartcard controller,
● two ASCs (UARTs) which are generally used by the smartcard controllers or for modem
application,
● two SSCs for I²C master/slave interfaces, with SPI support,
● four GPIO ports,
● infrared blaster/decoder interface module,
● DVB common interface support,
● a fully integrated digital VCXO,
● an interrupt level controller,
● a low-power/RTC/watchdog controller,
● DCU toolset support,
● a JTAG/TAP interface.
2.12
Clock generation
All system clocks are generated using the clock generator block. This contains two
high-frequency PLLs (532 MHz/400 MHz) that are divided down to produce a series of
phase-related programmable clock channels.
The STi5107 has a clock master. The Flash clock output may be phase aligned to optimize
the external bus performance of the FMI.
VCXO functionality has been integrated using a special purpose frequency synthesizer, thus
removing the need for an external varactor diode or VCXO module.
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