STLC2415 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STLC2415' PDF : 22 Pages View PDF
STLC2415
including internal decimator and interpolator filters. The data can be linear PCM (13-16bit), µ-Law (8bit) or
A-Law (8bit). By default the codec interface is configured as master. The encoding on the air interface is
programmable to be CVSD, A-Law or µ-Law.
The PCM block is able to manage the PCM bus with up to 3 timeslots.
In master mode, PCM clock and data can operate at 2 MHz or at 2.048 MHz to allow interfacing of stan-
dard codecs.
The four signals of the PCM interface are:
– PCM_CLK : PCM clock
– PCM_SYNC : PCM 8kHz sync
– PCM_A : PCM data
– PCM_B : PCM data
Directions of PCM_A and PCM_B are software configurable.
Figure 6. PCM (A-law, µ-law) Standard Mode
PCM_CLK
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
PCM_SYNC
PCM_A
PCM_B
B
B
125µs
B
B
D02TL558
Figure 7. Linear Mode
PCM_CLK
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
PCM_SYNC
PCM_A
PCM_B
125µs
D02TL559
Table 11. PCM Interface Timing.
Symbol
Description
PCM Interface
Fpcm_clk Frequency of PCM_CLK (master)
Fpcm_sync Frequency of PCM_SYNC
tWCH High period of PCM_CLK
tWCL Low period of PCM_CLK
tWSH High period of PCM_SYNC
tSSC Setup time, PCM_SYNC high to PCM_CLK low
tSDC Setup time, PCM_A/B input valid to PCM_CLK low
tHCD Hold time, PCM_CLK low to PCM_A/B input invalid
tDCD Delay time, PCM_CLK high to PCM_A/B output valid
Min
Typ
Max Unit
-
2048
kHz
8
kHz
200
ns
200
ns
200
ns
100
ns
100
ns
100
ns
150
ns
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