STLC2416
10 HCI USB TRANSPORT LAYER
The USB Transport Layer has been specified by the Bluetooth™ SIG, and allows HCI level communica-
tion between a host controller (STLC2416) and a host (e.g. PC), via a USB interface. The USB Transport
Layer is completely implemented in SW. It accepts HCI messages from the HCI Layer, prepares it for
transmission over a USB bus, and sends it to the USB Driver. It reassembles the HCI messages from USB
data received from the USB Driver, and sends these messages to the HCI Layer. The Transport Layer
does not interprete the contents (payload) of the HCI messages; it only examines the header.
11 CLASS1 POWER SUPPORT
The chip can control an external power amplifier (PA). Several signals are duplicated on GPIOs for this
purpose in order to avoid digital/analogue noise loops in the radio.
A software controlled register enables the alternate functions of GPIO[15:6] to generate the signals for
driving an external PA in a Bluetooth™ class1 power application.
Every bit enables a dedicated signal on a GPIO pin, as described in Table 14.
12 GPIOS
Table 14. GPIOs alternate functionalities
Involved GPIO
gpio0
gpio1
gpio2
gpio3
gpio4
gpio5
gpio6
gpio7
gpio8
gpio9
gpio10
gpio11
gpio12
gpio13
gpio14
gpio15
Description of alternate dedicated functionality
No dedicated function
WLAN 1
WLAN 2
WLAN 3
WLAN 4
(Used for USB reset pull.)
Power Class 1 brxen
Power Class 1 not_brxen
Power Class 1 PA0 or PCM sync 1
Power Class 1 PA1 or PCM sync 2
Power Class 1 PA2 or PCM sync 3
Power Class 1 PA3
Power Class 1 PA4
Power Class 1 PA5
Power Class 1 PA6
Power Class 1 PA7
The signal brxen is the same as the brxen radio output pin. The signal not_brxen is the inverted signal, in
order to save components on the application board.
PA7 to PA0 are the power amplifier control lines. They are managed, on a connection basis, by the base-
band core. The Power Level programmed for a certain Bluetooth™ connection is managed by the firm-
ware, as specified in the Bluetooth™ SIG spec.
The WLAN signals, as described in section 7.12, can be enabled on GPIO pins.
The extra PCM sync signals, as described in section 8.7, can be flexibly configured on GPIO pins to con-
nect multiple codecs.
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