STLC5046
Static I/O mode:
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
CIO3 CIO2 CIO1 CIO0
CIO0..3=0 The CS0..3 is a static input, DATA is
written in DATA2 register bits 0..3.
CIO0..3=1 The CS0..3 is a static output, DATA is
taken from DATA2 register bits 0..3.
Pin strap value:
0
0
0
0
0
0
0
0
0
0
0
0
I/O Data Register channel #2 (DATA2)
Addr=07h; Reset Value=00h
Addr=08h; Reset Value=X0h
If bit 4 of CONF register (STA)=0
Dynamic I/O mode:
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
D27 D26 D25 D24 D23 D22 D21 D20
D211 D210 D29 D28
When CS2 is active D211..0 are transferred to the
corresponding I/O pins configured as outputs
(see DIR register). For the I/O pins configured as
inputs the corresponding D11..0 will be written by
the values applied to those pins while CS2 is low.
If bit 4 of CONF register (STA)=1
Static I/O mode:
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
CD3 CD2 CD1 CD0
CD3..0 are transferred to the corresponding CS
pin if configured as static output (see register
DATA1). For the CS pins configured as static in-
puts the corresponding CD3..0 will be written by
the values applied to those pins.
Pin strap value:
0
0
0
0
0
0
0
0
0
0
0
0
I/O Data Register channel #3 (DATA3)
Addr=09h; Reset Value=00h
Addr=0Ah; Reset Value=X0h
Used only if bit 4 of CONF register (STA)=0; Dy-
namic I/O mode:
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
D37 D36 D35 D34 D33 D32 D31 D30
D311 D310 D39 D38
When CS3 is active D11..0 are transferred to the
corresponding I/O pins configured as outputs
(see DIR register). For the I/O pins configured as
inputs the corresponding D11..0 will be written by
the values applied to those pins while CS3 is low.
If bit4 of CONF register (STA)=1
Static I/O mode:
can be used as general purpose R/W registers,
without any direct action on the control of the de-
vice.
Pin strap value:
0
0
0
0
0
0
0
0
0
0
0
0
Transmit Gain channel #0 (GTX0)
Addr=0Bh; Reset Value=00h
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
00h:Stop any trasmit signal, null level is transmit-
ted in the corresponding timeslot on DX output.
>00h:Digital gain is inserted in the TX path equal
to:
20log[0.25+0.75*(progr.value/256)]
Pin strap values:
GX0=1: 0dB gain (value = FFh):
1
1
1
1
1
1
1
1
GX0=0: -3.5dB gain (value = 8Fh):
1
0
0
0
1
1
1
1
Transmit Gain channel #1 (GTX1)
Addr=0Ch; Reset Value=00h
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
12/27
00h:Stop any trasmit signal, null level is transmit-