STLC5460 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STLC5460' PDF : 54 Pages View PDF
STLC5460
M0D
TIMD
ISPM
MOD
DCKM
Multiplex 0 Disable.
M0D = 1. Multiplex 0 output is at high impedance continuously,
multiplex 0 input is forced to ”1”, if it is GCI.
Timer Monitor Channel Disabled.
TIMD = 1. The timer 1ms is disabled for each Transmit Monitor Channel.
Input Sampling Multiplex.
ISPM = 0. The input bit is sampled at half bit time.
ISPM = 1. The input bit is sampled at 3/4 bit time.
Multiplex Open Drain.
MOD = 1. The two multiplex outputs are open drain.
MOD = 0. The two multiplex outputs are at low impedance
Double clock for Multiplex.
DCKM = 1. DCL is twice data rate (Ex : if Data Rate = 2048 kb/s,DCL = 4096 kHz).
DCKM = 0. DCL is simple clock.
PCM CONFIGURATION REGISTER (PCONF)
7
0
TSNB
DEL
PFSP
ODL
After Reset 00 (H)
ISPP
POD
0
SCKP
TSNB
DEL
PFSP
ODL
ISPP
POD
SCKP
Time Slot numbering.
TSNB defines the order of TS on the PCM when the data rate is 4 Mb/s or 8 Mb/s
related to the order of TS on the PCM at 2 Mb/s (see table hereafter).
Delayed Mode for each PCM.
DEL = 1. A delay of one clock pulse is applied to the first bit of the frame of each PCM.
DEL = 0. PFS indicates the first bit of the frame for each PCM (if OFFSET and shift are
zero).
PCM Frame Synchronisation Sampling.
PFSP = 0. PFS signal is sampled on the fall edge of PDC signal.
PFSP = 1. PFS signal is sampled on the rise edge of PDC signal.
Output Delay.
ODL = 0. The bits are shifted out with zero delay.
ODL = 1. The bits are shifted out with a delay of one half bit time.
Input Sampling PCM.
ISPP = 0. The input bit is sampled at half bit time.
ISPP = 1. The input bit is sampled at 3/4 bit time.
PCM Open Drain.
POD = 1. The PCM outputs are open drain
POD = 0. The PCM outputs are at low impedance.
Simple clock for PCM.
SCKP = 0. PDC signal is twice data rate. (Ex : if data rate = 2048 kb/s, PDC = 4096
kHz).
SCKP = 1. PDC is simple clock
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