APPENDIX
STLC5460
MEMORY ACCESSES
COMMAND MEMORY ACCESSES. CM=1
Write Command Memory:
CMD and SRC registers are written if their bits have not the right value.
CMD and SRC registers can be written in any order.
DST register is always written the last
CMD
SRC
R CM Subchannel select
0 1 and data rate
1 of 192 input timeslots
1 of 2 insert registers
R=0 Write 6
CM=1 Command
Memory
IN
8
IN
Command Memory
A
194 words of 14 bits
DST
1 of 192 output timeslots
1 of 2 extract registers
8
Read Command Memory in two steps:
First step: register writing
CMD register is written if its bits are not the right value.
SRC register is not written.
DST register is always written the last.
CMD
SRC
DST
R CM
11
bits not used
Register not written
1 of 192 output timeslots
1 of 2 extract register
2
8
Command Memory
194 words of 14 bits
A
OUT
OUT
6
8
R CM selected channel
1 1 and data rate
1 of 192 input timeslots
1 of 2 insert registers
1 of 192 output timeslots
1 of 2 extract register s
CMD
SRC
Second step: register reading:
CMD and SRC registers may be read in any order.
DST register is not changed.
DST
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