STLC5460
MEMORY ACCESS ALGORITHM
Figure 4: Control or Auxiliary Memory Accesses
WRITE MEMORY
Read Status Register
BUSY
Ye s
No
Writ e Co m m a n d R e g is te r
w ith R /W=0
Writ e S ou rce R e gis t e r
Write D e s tin ation Re g is te r
END
READ MEMORY
Read Status Register
BUSY
Yes
No
Writ e Co mm a n d R e gis te r
w ith R/W=1
Write D e s tin a tio n R e g is te r
Read Status Register
BUSY
Ye s
No
Read Command Register
(option al)
Read Source Register
Read Destination Register
(option al)
END
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