STLC5460 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STLC5460' PDF : 54 Pages View PDF
STLC5460
Figure 1: PCM Interface. Alignment in double clock mode.
Mode not delayed:
PFS
DCL=1
DEL=0
PFSP=0
PDC
DCL=1
DEL=0
PFSP=1
PFS
PDC
Mode delayed:
PFS
DCL=1
DEL=1
PFSP=0
PDC
DCL=1
DEL=1
PFSP=1
PFS
PDC
Clocks received by the circuit
First bit of the frame
First bit of the frame
First bit of the frame
First bit of the frame
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