STM32F373xx
Electrical characteristics
6.3.3
Embedded reset and power control block characteristics
The parameters given in Table 24 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 22.
Table 24. Embedded reset and power control block characteristics
Symbol
Parameter
Conditions
Min Typ Max
VPOR/PDR(1)
Power on/power down
reset threshold
Falling edge
Rising edge
1.80(2) 1.88 1.96
1.84 1.92 2.00
VPDRhyst(3) PDR hysteresis
tRSTTEMPO(3) POR reset temporization
-
-
40 -
-
1.50 2.50 4.50
1.
The PDR detector monitors
detector monitors only VDD.
VDD,
VDDA
and
VDDSD12
(if
kept
enabled
in
the
option
bytes).
The
POR
2. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.
3. Guaranteed by design.
Unit
V
V
mV
ms
Symbol
Table 25. Programmable voltage detector characteristics
Parameter
Conditions
Min(1) Typ Max(1) Unit
VPVD0
PVD threshold 0
VPVD1
PVD threshold 1
VPVD2
PVD threshold 2
VPVD3
PVD threshold 3
VPVD4
PVD threshold 4
VPVD5
PVD threshold 5
VPVD6
PVD threshold 6
VPVD7
PVD threshold 7
VPVDhyst(2)
IDD(PVD)(2)
PVD hysteresis
PVD current
consumption
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
-
-
2.10 2.18 2.26 V
2.00 2.08 2.16 V
2.19 2.28 2.37 V
2.09 2.18 2.27 V
2.28 2.38 2.48 V
2.18 2.28 2.38 V
2.38 2.48 2.58 V
2.28 2.38 2.48 V
2.47 2.58 2.69 V
2.37 2.48 2.59 V
2.57 2.68 2.79 V
2.47 2.58 2.69 V
2.66 2.78 2.9
V
2.56 2.68 2.8
V
2.76 2.88 3.00 V
2.66 2.78 2.90 V
-
100
-
mV
-
0.15 0.26 µA
1. Guaranteed by characterization results.
2. Guaranteed by design.
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