STM8AP6268TA View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
STM8AP6268TA
STMicroelectronics
'STM8AP6268TA' PDF : 89 Pages View PDF
Electrical characteristics
STM8AF61xx, STM8AF62xx
4. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
5. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.
Figure 37. SPI timing diagram where slave mode and CPHA = 0
NSS input
tSU(NSS)
CPHA= 0
CPOL=0
CPHA= 0
CPOL=1
tw(SCKH)
tw(SCKL)
ta(SO)
MISO
OUT P UT
tsu(SI)
MOSI
I NPUT
tc(SCK)
tv(SO)
MS B O UT
M SB IN
th(SI)
th(SO)
BI T6 OUT
B I T1 IN
th(NSS)
tr(SCK)
tf(SCK)
tdis(SO)
LSB OUT
LSB IN
1. Measurement points are at CMOS levels: 0.3 VDD and 0.7 VDD.
Figure 38. SPI timing diagram where slave mode and CPHA = 1
ai14134
NSS input
tSU(NSS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tw(SCKH)
tw(SCKL)
MISO
OUT P UT
MOSI
I NPUT
ta(SO)
tsu(SI)
tc(SCK)
tv(SO)
MS B O UT
th(SI)
M SB IN
th(SO)
BI T6 OUT
B I T1 IN
1. Measurement points are at CMOS levels: 0.3 VDD and 0.7 VDD.
th(NSS)
tr(SCK)
tf(SCK)
tdis(SO)
LSB OUT
LSB IN
ai14135
66/89
Doc ID 14952 Rev 6
Share Link: 