STM8S103C2P6 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
STM8S103C2P6
STMicroelectronics
'STM8S103C2P6' PDF : 56 Pages View PDF
Product overview
4
Product overview
STM8S103xx, STM8S105xx
The following section intends to give an overview of the basic features of the
STM8S103/105 access line functional modules and peripherals.
For more detailed information please refer to the corresponding family reference manual
(RM0016).
4.1
Central processing unit STM8
The 8-bit STM8 core is designed for code efficiency and performance.
It contains 6 internal registers which are directly addressable in each execution context, 20
addressing modes including indexed indirect and relative addressing and 80 instructions.
Architecture and registers
ā Harvard architecture
ā 3-stage pipeline
ā 32-bit wide program memory bus - single cycle fetching for most instructions
ā X and Y 16-bit index registers - enabling indexed addressing modes with or without
offset and read-modify-write type data manipulations
ā 8-bit accumulator
ā 24-bit program counter - 16-Mbyte linear memory space
ā 16-bit stack pointer - access to a 64 K-level stack
ā 8-bit condition code register - 7 condition flags for the result of the last instruction
Addressing
ā 20 addressing modes
ā Indexed indirect addressing mode for look-up tables located anywhere in the address
space
ā Stack pointer relative addressing mode for local variables and parameter passing
Instruction set
ā 80 instructions with 2-byte average instruction size
ā Standard data movement and logic/arithmetic functions
ā 8-bit by 8-bit multiplication
ā 16-bit by 8-bit and 16-bit by 16-bit division
ā Bit manipulation
ā Data transfer between stack and accumulator (push/pop) with direct stack access
ā Data transfer using the X and Y registers or direct memory-to-memory transfers
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