STM8S103K3 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
STM8S103K3
STMicroelectronics
'STM8S103K3' PDF : 56 Pages View PDF
STM8S103xx, STM8S105xx
Product overview
Note:
4.14.3
LIN slave
ā Autonomous header handling - one single interrupt per valid message header
ā Automatic baud rate synchronization - maximum tolerated initial clock deviation Ā±15 %
ā Synch delimiter checking
ā 11-bit LIN synch break detection - break detection always active
ā Parity check on the LIN identifier field
ā LIN error management
ā Hot plugging support
Asynchronous communication (UART mode)
ā Full duplex, asynchronous communications - NRZ standard format (mark/space)
ā Independently programmable transmit and receive baud rates up to 500 Kbit/s
ā Programmable data word length (8 or 9 bits)
ā Low-power standby mode - 2 receiver wake-up modes:
ā Address bit (MSB)
ā Idle line
ā Muting function for multiprocessor configurations
ā Overrun, noise and frame error detection
ā 6 interrupt sources
ā Tx, Rx parity control
In STM8S105, the LINUART also supports IrDA mode, Smartcard mode and synchronous
communication (SPI master mode).
SPI
ā Maximum speed: 8 Mbit/s (fMASTER/2) both for master and slave
ā Full duplex synchronous transfers
ā Simplex synchronous transfers on 2 lines with a possible bidirectional data line
ā Master or slave operation - selectable by hardware or software
ā CRC calculation
ā 1 byte Tx and Rx buffer
ā Slave/master selection input pin
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