STN1110 View Datasheet(PDF) - Unspecified
Part Name
Description
MFG CO.
'STN1110' PDF : 22 Pages View PDF
STN1110
4.2 Detailed Pin Descriptions
R¯E¯¯S¯E¯T
Device reset input. A logic low pulse (min 2 μs) on this
pin will reset the device. Apply a continuous logic low
to hold the device in reset. If your circuit does not use
this functionality, connect this pin to VDD.
ANALOG_IN
Analog voltage measurement input (AVDD max). By
default, this input is calibrated for an external
62kΩ/10kΩ voltage divider connected to battery
positive. Connect to AVSS if unused.
PWM / ¯V¯P¯W¯
The firmware uses this pin to control the voltage level
of the SAE J1850 PWM/VPW Bus+ supply. When the
PWM protocol is selected, it outputs a logic high to
switch the supply voltage to a nominal 5V. When the
VPW protocol is selected, it outputs a logic low to
switch the supply voltage to a nominal 8V. Leave
unconnected if unused.
¯V¯P¯W¯_¯R¯X¯
Active low SAE J1850 VPW receive input. When the
SAE J1850 Bus+ is in the recessive (low) state, this
pin should be at a logic high level. When the
SAE J1850 Bus+ is in the dominant (high) state, this
pin should be at a logic low level. Pull up to VDD if
unused.
PWM_RX
SAE J1850 PWM receive input. When the SAE J1850
bus is in the recessive state (Bus+ is low, Bus- is
high), this pin should be at a logic low level. When the
SAE J1850 bus is in the dominant (Bus+ is high)
state, this pin should be at a logic high level. Pull up to
VDD if unused.
J1850_BUS+_TX
SAE J1850 Bus+ transmit output. When the pin is
high, Bus+ should be high (dominant). Leave
unconnected if unused.
J¯1¯8¯5¯0¯_¯B¯U¯S¯-¯_¯T¯X
Active low SAE J1850 Bus- transmit output. When the
pin is high, Bus- should be low (dominant). Leave
unconnected if unused.
VSS
Ground reference for logic and I/O pins.
OSC1, OSC2
16.000 MHz oscillator crystal connection.
I¯S¯O¯_¯R¯X¯
Active low ISO 9141/ISO 14230 K-line receive input.
When K-line is high (recessive), this pin should be at a
logic low level. Connect to VSS if unused.
S¯L¯E¯¯E¯P
External sleep control input. When enabled in
firmware, puts the device into low-power sleep mode.
Polarity of this pin can be configured in firmware;
default configuration is active low. Internal pull-up to
VDD is enabled by default, but can be disabled in
firmware. Leave unconnected if unused.
VDD
Positive 3.0 – 3.6V supply for logic and I/O pins.
CAN_RX
CAN receive input. Must be connected to a CAN
transceiver IC. Compatible with +3.3V and +5V logic.
Pull up to VDD if unused.
CAN_TX
CAN transmit output. Must be connected to a CAN
transceiver IC. Open drain – requires a pull-up to VDD
or +5V (12 mA max). Pull-up resistor value depends
on CAN baud rates used and the trace length (higher
resistor values can be used with lower baud rates and
shorter traces); recommended value is 1 kΩ. Pull up
to VDD via 100 kΩ resistor if unused.
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STN1110DSA
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