HCLK
PA[ ] bus
CSx#
PWR#[1:0]
PD[15:0]
ELECTRICAL SPECIFICATIONS
Figure 4-10. Synchronous Write Cycle
Tsetup
Tactive
Thold
HCLK
PA[ ] bus
CSx#
PWR#[1:0]
PD[15:0]
PRDY
Figure 4-11. Asynchronous Write Cycle
Tsetup
Tend
Thold
Release 1.5 - January 29, 2002
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