STPCC4 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STPCC4' PDF : 93 Pages View PDF
DESIGN GUIDELINES
In the case of higher clock load it is recommended
to use a zero-delay clock buffer as described in
Figure 6-8. This approach is also recommended
when implementing the delay on PCICLKI
according to the PCI section of the Electrical
Specifications chapter.
Figure 6-8. PCI clock routing with zero-delay clock buffer
PCICLKI
PCICLKI
PCICLKO
PLL
CY2305
Device A
Device B
Device C
Device D
Implementation 1
PCICLKO
PLL
CY2305
Device A
Device B
Device C
Device D
Implementation 2
Release 1.5 - January 29, 2002
69/93
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