STV0299B View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STV0299B' PDF : 36 Pages View PDF
STV0299B
6 ELECTRICAL CHARACTERISTICS (continued)
6.4 Timing Characteristics
Symbol Parameter
Min.
Typ.
Max.
fVCO
Internal VCO frequency
300
400
fCLK_IN
CLK_IN or XTAL frequency
4
30
PARALLEL OUTPUT D[7:0], D/P, CLK_OUT, STR_OUT, ERROR OUTPUT CHARACTERISTICS
Bit RS1 = 1 in RS CONTROL REGISTER (Address 33). Refer to Figure 8
tCLK_duty
CLK_OUT duty cycle
40
50
60
tCKSU
D[7:0], D/P, STR_OUT, ERROR stable before CLK_OUT
Falling Edge
2*Tm(1)
tCKH
D[7:0], D/P, STR_OUT, ERROR stable after CLK_OUT
Falling Edge
2*Tm(1)
Unit
MHz
MHz
%
ns
ns
Bit RS1 = 0 in RS CONTROL REGISTER (Address 33). Refer to Figure 9
tCKSU
D[7:0], D/P, STR_OUT, ERROR stable before CLK_OUT
Falling Edge
2*Tm(1)
ns
tCKH
D[7:0], D/P, STR_OUT, ERROR stable after CLK_OUT
Falling Edge
2*Tm(1)
ns
SERIAL OUTPUT D7, D/P, CLK_OUT, STR_OUT, ERROR OUTPUT CHARACTERISTICS
Bit RS1 = 1 in RS CONTROL REGISTER (Address 33). fM.CLK = 90MHz. Refer to Figure 10
tCKSU
D7, D/P, STR_OUT, ERROR stable before CLK_OUT
Falling Edge
3.5
ns
tCKH
D7, D/P, STR_OUT, ERROR stable after CLK_OUT
Falling Edge
3
ns
Bit RS1 = 0 in RS CONTROL REGISTER (Address 33). fM.CLK = 90MHz. Refer to Figure 11
tCKSU
D7, D/P, STR_OUT, ERROR stable before CLK_OUT
Falling Edge
3.5
ns
tCKH
D7, D/P, STR_OUT, ERROR stable after CLK_OUT
Falling Edge
2
ns
Note: 1 Tm = Master clock period in ns
Figure 8:
Figure 10:
CLK_OUT
CLK_OUT
D[7:0], D/P.
STR_OUT,
ERROR
tCKSU
tCKH
D7, D/P.
STR_OUT,
ERROR
tCKSU
tCKH
Figure 9:
CLK_OUT
D[7:0], D/P.
STR_OUT,
ERROR
tCKSU
tCKH
Figure 11:
CLK_OUT
D7, D/P.
STR_OUT,
ERROR
tCKSU
tCKH
31/36
Share Link: 
