STV8268FD View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STV8268FD' PDF : 157 Pages View PDF
I²S Interface (In / Out)
.
Figure 27: TQFP 80 I²S Output Block Diagram
STV82x8
I2S_DATA0
fS Output = 48 kHz
I2S_SCLK
fS Output * 64
I2S_LR_CLK
fS Output = 48 kHz
I2S_PCM_CLK
Audio Processing
48 kHz DSP
Processing
6.2.2
I²S Outputs in TQFP 100 Package
Two digital stereo outputs (I²S compatible) are available for routing the demodulated signal or a
converted input audio signal to an external device or perform an external delay. In this case, the
I2SO_DATA0 and I2SO_DATA1 signals are available with all I²S inputs active. The STV82x8 drives
the serial bus (I2SO_SCLK,I2SO_LR_CLK, I2SO_DATA0, and I2SO_DATA1) in master mode in
64.fs format with a sampling frequency (fs) of 48 kHz. The I2S_PCM_CLK signal can be used as a
master clock if required for the slave interface. Both standard and non-standard modes are
available. .
Figure 28: TQFP100 I²S Output Block Diagram
I2SO_DATA0
fS Output = 48 kHz
I2SO_DATA1
fS Output = 48 kHz
I2SO_SCLK
fS Output * 64
I2SO_LR_CLK
fS Output = 48 kHz
I2S_PCM_CLK
Audio Processing
48 kHz DSP
Processing
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