STV8287D View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
STV8287D
STMicroelectronics
'STV8287D' PDF : 149 Pages View PDF
STV82x7
I²S Interface (In / Out)
Table 6: I²S Frequency Configuration
I²S
(Max. Number of Channels)
1 (I²S_DATA0)
1 (I²S_DATA0)
3
1 (I²S_DATA0)
1 (I²S_DATA0)
3
1 (I²S_DATA0)
1 (I²S_DATA0)
3
fS Input (kHz)
8
16
32
11.025
22.05
44.1
12
24
48
fS Output (kHz)
after SRC
32.0
32.0
32.0
44.1
44.1
44.1
48.0
48.0
48.0
SRC Use
x4
x2
No
x4
x2
No
x4
x2
No
Both standard and non-standard modes are available, see Figure 26.
6.2 I²S Output
Note:
A digital stereo output (I²S compatible) is also available for routing the demodulated signal or a
converted input audio signal to an external device. In this case the I²S_DATA0 signal and all clock
signals are set as outputs by setting bit D6 in register RESET to 1. The STV82x7 I²S drives the
serial bus (SCLK, LR_CLK, I²S_DATA0) in master mode in 64.fs format with a sampling frequency
(fs) of 32 kHz. The I²S_PCM_CLK signal can be used as a master clock in 512.fs format if required
for the slave interface. Both standard and non-standard modes are available, see Figure 26.
The Input and Output modes for I²S are exclusive.
Figure 26: I²S Data Format: Lch = LOW, Rch = HIGH (I²S Input or Output mode)
I²S_LR_CLK
I²S_SCLK
(= 64fs)
I²S_DATAx
(standard mode)
I²S_DATAx
(non-standard mode)
12 3
MSB
12 3
MSB
1/fs
Lch
Rch
22 23 24
LSB
22 23 24
LSB
123
MSB
123
MSB
22 23 24
LSB
22 23 24
LSB
12
123
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