STV82X6 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STV82X6' PDF : 97 Pages View PDF
Register List
STV82x6
Bit Name
Reset
Function
Bit7
SCLPD_OFF
AUTO_OFF
Bits[4:3]
0 Reserved.
SCL Pulling-down System Disable
0: System is enabled
1: System is disabled
0 Automatic Standard Recognition System Disable
0: System is enabled
1: System is disabled
00 Reserved.
SOFT_LRESTART1
SOFT_LRESTART2
SOFTRST
0 Softreset (active high) of Channel 1 detectors only.
0 Softreset (active high) of Channel 2 detectors only.
0 General softreset (active high) to reset all hardware registers except for I²C data.
CTRL
Hardware Interface Control Register
Address (hex): 03h
Type: R/W
Bit 7
Bit 6
Bit 5
0
BUS_EXPAND[1:0]
Bit 4
I2S_EN
Bit 3
SDI_EN
Bit 2
0
Bit 1
MCK_EN
Bit 0
SYSCK_EN
Description
Provides all hardware controls to drive external components (SAW Filter, Audio Switches) and
additional Audio Decoder (Dolby Pro Logic) via register I2S including the Master and Quartz Clocks.
Bit Name
Reset
Function
Bit 7
0 Reserved.
BUS_EXPAND[1:0]
I2S_EN
SDI_EN
00 Static control by I²C of hardware pins BUS1 and BUS0.
0 When 1, the I²S hardware pin is enabled (SCK, WS, SDO)
0 When 1, the SDI input pin is enabled (switch with ST output). Must be used when I²S mode is
selected.
Bit 2
MCK_EN
SYSCK-EN
0 Reserved.
0 Master Clock Enable
Enables the master clock output (256.fs) to interface by I²S with the Dolby Pro Logic Decoder.
0: Disabled.
1: Enabled
0 System Clock Enable
Enables the system clock output to provide the quartz clock required to interface with the Dolby Pro
Logic Decoder.
0: Disabled.
1: Enabled
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