STV9410 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STV9410' PDF : 25 Pages View PDF
STV9410
TIMINGS
(VDD = 5V ±5%, VSS = 0V, Ta = 0 to + 70oC, fxtal = 8 to 10MHz,
VIL = 0.8V, VIH = 2V, VOL = 0.4V, VOH = 2.4V, CL = 50pF, unless otherwise specified)
Symbol
Parameter
Min
Typ
SERIAL INTERFACE NCS, SCK, SDA (Figure 1)
Tcsl
Tsch
Tscl
fSCK
Tsds
Tsdh
Tsdv
Tsdx
Tsdz
Tread
NCS low to SCK falling edge
SCK pulse width high
SCK pulse width low
Serial Clock Frequency
Set up time of SDA on SCK rising edge
Hold time of SDA after SCK rising edge
Access time in read mode
Hold data in read mode
Serial interface disable time
Delay before Valid Data
OSCILLATOR INPUT (XTI) (Figure 1)
0
80
80
20
20
50
0
50
2
Twh
Clock high level
30
T wl
Clock low level
30
Fclk
Clock frequency
8
RESET (VREF)
Tres
Reset Low level pulse
2
OUTPUT SIGNALS SDA, CSYNC, VSYNC, R, G, B, I, SYNC IN, DF, XTO, CKO, POR (Figure 2)
Tp h,Tpl
Propagation time
CL = 30 pF
CL = 100 pF
Tskew
Skew between R, G, B, I signals
(VDD = 5V ±5%, VSS = 0V, Ta = 0 to + 70oC, fxtal = 8 to 10MHz,
VOL = 0.2VDD, VOH = 0.8VDD, CL = 100pF, unless otherwise specified)
LCD INTERFACE D0, D1, D2, D3, CKD, LOAD, DF, FRAME (Figure 3)
tCYC
CKD Shift Clock Period
tCH
CKD Clock High
tCL
CKD Clock Low
tWLD
Load Pulse Width
tSU
Data Set-up Time
tDH
Data Hold Time
tDF
DF Delay from Load
tSUF
Frame Set-up before Load
4 x Pxtal
150
150
150
150
150
150
Max Unit
ns
ns
ns
4
MHz
ns
ns
ns
ns
ns
µs
ns
ns
10 MHz
µs
50
ns
100
ns
30
ns
ns
ns
ns
ns
ns
ns
100
ns
ns
5/25
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