STV9432 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'STV9432' PDF : 18 Pages View PDF
STV9432
Locking Condition Time Constant (@ 4035)
This register provides the AS[2:0] and BS[2:0]
constants used by the algo part of the PLL (see
Figure 6). These two constants as well as the
phase error (err(n)) give the new value (Dn) of the
high frequency signal division. Consequently,
AS[2:0] and BS[2:0] fix the pixel clock frequency.
These two constants are used only in locking con-
dition, if the phase error is inferior to a fixed value
during at least 4 scan lines. If the phase error
becomes superior to the fixed value, the PLL is
not in locking condition but in capture process. In
this case, the algo part of the PLL uses the other
constants AF[2:0] and BF[2:0] from the next regis-
ter.
Capture Process Time Constant (@ 4036)
The choice between these two time constants
(locking condition or capture process) allows to
decrease the capture process time by changing
the time response of the PLL.
8.5.2 - How to choose the time constant value
The time response of the PLL is given by its char-
acteristic equation which is:
(x - 1)2 + ( α + β ) . (x - 1) + β = 0
Where:
α = 3 ⋅ LD[6:1] . 2A -11 and β = 3 . LD[6:1] . 2B - 19
(LD[6:1] = value of the LINE DURATION register,
A = value of the 1st time constant, AF or AS and
B = value of the 2d time constant, BF or BS).
As can be seen, the solution depends only on the
LINE DURATION and the TIME CONSTANTS
given by the I2C registers.
Table 3 Valid Time Constants Examples
B\A
0
1
2
0
YYYY
YYYY
YYYY
1
YYYY
YYYY
YYYY
2
NYYY
YYYY
YYYY
3
NNNY
YYYY
YYYY
4
NNNN
NYYY(1)
YYYY
5
NNNN
NNNY
YYYY
6
NNNN
NNNN
NYYY
7
NNNN
NNNN
NNNY
If ( α + β )2 - 4 β ≥ 0 and 2 α – β < 4, the PLL is sta-
ble and its response is as shown in Figure 15.
If ( α + β )2 - 4 β ≤ 0 , the response of the PLL is as
shown in Figure 9. In this case the PLL is stable if
τ > 0.7 damping coefficient.
Table 3 gives some good values for A and B con-
stants for different values of the LINE DURATION.
Figure 8. Time Response of the PLL/
Characteristic equation solutions (with real
solutions)
PLL Frequency
f1
f0
t
Input Frequency
f1
f0
t
Figure 9. Time Response of the PLL/
Characteristic equation solutions (with
complex solutions)
PLL Frequency
f1
f0
t
Input Frequency
f1
f0
t
3
YYYN
YYYN
YYYN
YYYN
YYYN
YYYN
YYYN
YYYN
4
YNNN
YNNN
YNNN
YNNN
YNNN
YNNN
YNNN
YNNN
5
NNNN
NNNN
NNNN
NNNN
NNNN
NNNN
NNNN
NNNN
6
NNNN
NNNN
NNNN
NNNN
NNNN
NNNN
NNNN
NNNN
Notes: - Table meaning: N = No possible capture - No stability, Y = PLL can lock.
- Case of A[2:0] = 1 (001) and B[2:0] = 4 (100):
LD[6:1]
Valid Time Constants
8
16
24
32
N
Y
Y
Y
15/18
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