STV9432TAP View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
STV9432TAP
STMicroelectronics
'STV9432TAP' PDF : 25 Pages View PDF
STV9432TAP
12.3 - OSD TIMINGS
The number of pixel periods is given by the LINE
DURATION register and is equal to:
[LD[6:1] x 2 + 1 ] x 12.
(LD[6:1]: value of the LINE DURATION register).
This value allows to define the horizontal size of
the characters.
The horizontal left margin is given by the HORI-
ZONTAL DELAY register and is equal to:
(DD[7:0] -6) x 6 + 54
(DD[7:0]: value of the DISPLAY DELAY register).
This value allows to define the horizontal position
of the characters on the screen. Due to internal
logic, minimum horizontal delay is fixed at 4.5
characters (54 pixel) when DD is even and lower
or equal to 6, and it is fixed at 5 characters (60
pixel) when DD is odd and lower or equal to 7.
12.4 - PLL
The PLL function of the STV9432TAP provides
the internal pixel clock locked on the horizontal
synchro signal and used by the display processor
to generate the R, G, B and fast blanking signals.
It is made of 2 PLLs. The first one analog (see Fig-
ure 11) provides a high frequency that is 40 times
the internal oscillator frequency, or 320MHz. This
high frequency clock is used by the Display con-
troller.
The 320MHz frequency is then divided by three.
The resulting 106.7MHz clock is used by the
Video timings analysis block.
The second PLL, full digital (see Figure 12), pro-
vides a pixel frequency locked on the horizontal
synchro signal. The ratio between the frequencies
of these 2 signals is:
M = 12 x (LD[6:1] x 2 + 1) where LD[6:1] is the
value of the LINE DURATION register.
Figure 11. Analog PLL
VCO
40
N • fOSC
fOSC
FILTER
Figure 12. Digital PLL
40 •fOSC
%D
D(n)
%M
ALGO
M • fH-SYNC
fH-SYNC
err(n)
12.4.1 - Programming of the PLL Registers
Initial Pixel Period (@4037)
This register allows to increase the speed of the
convergence of the PLL when the horizontal fre-
quency changes (new graphic standard). The
relationship between PP[7:0], LD[6:1], fHSYNC and
fOSC is:
(
PP[7:0] = round
40 . fOSC
)
6 . (2 . LD + 1) . fHSYNC
Locking Condition Time Constant (@ 4035)
This register provides the AS[2:0] and BS[2:0]
constants used by the algo part of the PLL (see
Figure 11). These two constants as well as the
phase error err(n) give the new value D(n) of the
high frequency signal division. AS[2:0] and
BS[2:0] fix the pixel clock frequency. These two
constants are used only in locking condition, if the
phase error is inferior to a fixed value during at
least 4 scan lines. If the phase error becomes
greater than this fixed value, the PLL is not in lock-
ing condition but in capture process. In this case,
the algo part of the PLL used the other constants,
AF[2:0] and BF[2:0], given by the next register.
Capture Process Time Constant (@ 4036)
The choice between these two time constants
(locking condition or capture process) allows to
decrease the capture process time by changing
the time response of the PLL.
12.4.2 - How to choose the time constant value
The time response of the PLL is given by its char-
acteristic equation which is:
(x - 1)2 + (α + β ) . (x - 1) + β = 0
Where:
α = 3 ⋅ LD[6:1] . 2A -11 and β = 3 . LD[6:1] . 2B - 19
(LD[6:1] = value of the LINE DURATION register,
A = value of the 1st time constant, AF or AS and
B = value of the 2d time constant, BF or BS).
As you can see, the solution depends only on the
LINE DURATION and the TIME CONSTANTS
given by the I2C registers.
If (α + β )2 - 4 β ≥ 0 and 2 α – β < 4, the PLL is sta-
ble and its response is like that presented in Fig-
ure 14.
If ( α + β )2 - 4 β ≤ 0 , the response of the PLL is
like that presented in Figure 15. In this case the
PLL is stable if τ > 0.7 damping coefficient). Table
3 gives some good values for A and B constants
for different values of the LINE DURATION.
21/25
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