STW81103
SPI digital interface
Table 19. SPI data structure (MSB is sent first)
MSB
LSB
Address
Data for register (24 bits)
A1 A0 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Table 20. Address decoder and outputs
Address
A1 A0 DATABITS D23-D0 No Name
0
0
24
0
1
24
1
0
24
1
1
24
0
ST1
1
ST2
2
ST3
3
ST4
Outputs
Function
Reference divider, VCO amplitude, VCO calibration,
charge pump current, prescaler modulus
Functional modes, VCO dividers
Reserved
Reserved
7.2
Timing specification
Figure 27. SPI timing specification
tsetup thold
Data
Clock
Load
MSB
MSB-1
tdk
Table 21. SPI timing specification
Symbol
Parameter
tsetup
thold
tclk
tload
tclk_loadr
tclk_loadf
DATA to CLOCK setup time
DATA to CLOCK hold time
CLOCK cycle period
LOAD pulse width
CLOCK to LOAD rising edge
CLOCK to LOAD falling edge
LSB
tclk_loadf
t clk_loadr
tload
Min.
0.8
0.2
10
3
2
0.5
Typ.
Max.
Units
ns
ns
ns
ns
ns
ns
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