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SX1276 View Datasheet(PDF) - Semtech Corporation

Part Name
Description
MFG CO.
'SX1276' PDF : 132 Pages View PDF
SX1276/77/78/79
WIRELESS, SENSING & TIMING
DATASHEET
4.1.2. LoRaTM Digital Interface
The LoRaTM modem comprises three types of digital interface, static configuration registers, status registers and a FIFO
data buffer. All are accessed through the SX1276/77/78/79’s SPI interface - full details of each type of register are given
below. Full listings of the register addresses used for SPI access are given in Section 6.4.
4.1.2.1. LoRaTM Configuration Registers
Configuration registers are accessed through the SPI interface. Registers are readable in all device mode including Sleep.
However, they should be written only in Sleep and Standby modes. Please note that the automatic top level
sequencer (TLS modes) are not available in LoRaTM mode and the configuration register mapping changes as
shown in Table 41. The content of the LoRaTM configuration registers is retained in FSK/OOK mode. For the functionality
of mode registers common to both FSK/OOK and LoRaTM mode, please consult the Analog and RF Front End section of
this document (Section 5).
4.1.2.2. Status Registers
Status registers provide status information during receiver operation.
4.1.2.3. LoRaTM Mode FIFO Data Buffer
Overview
The SX1276/77/78/79 is equipped with a 256 byte RAM data buffer which is uniquely accessible in LoRa mode. This RAM
area, herein referred to as the FIFO Data buffer, is fully customizable by the user and allows access to the received, or to
be transmitted, data. All access to the LoRaTM FIFO data buffer is done via the SPI interface. A diagram of the user defined
memory mapping of the FIFO data buffer is shown below. These FIFO data buffer can be read in all operating modes
except sleep and store data related to the last receive operation performed. It is automatically cleared of old content upon
each new transition to receive mode.
Rev. 4 - March 2015
©2015 Semtech Corporation
Figure 8. LoRaTM Data Buffer
Page 34
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