T89C51AC2-SLSIM View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'T89C51AC2-SLSIM' PDF : 121 Pages View PDF
External Space
Memory Interface
External Bus Cycles
4127H–8051–02/08
A/T89C51AC2
The external memory interface comprises the external bus (port 0 and port 2) as well as
the bus control signals (RD, WR, and ALE).
Figure 13 shows the structure of the external address bus. P0 carries address A7:0
while P2 carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 17
describes the external memory interface signals.
Figure 13. External Data Memory Interface Structure
A/T89C51AC2
P2
ALE
P0
A15:8
AD7:0 Latch A7:0
RAM
PERIPHERAL
A15:8
A7:0
D7:0
RD
OE
WR
WR
Table 17. External Data Memory Interface Signals
Signal
Name
A15:8
AD7:0
ALE
RD
WR
Type Description
O
Address Lines
Upper address lines for the external bus.
Address/Data Lines
I/O Multiplexed lower address lines and data for the external
memory.
Address Latch Enable
O ALE signals indicates that valid address information are available
on lines AD7:0.
O
Read
Read signal output to external data memory.
O
Write
Write signal output to external memory.
Alternative
Function
P2.7:0
P0.7:0
-
P3.7
P3.6
This section describes the bus cycles the A/T89C51AC2 executes to read (see
Figure 14), and write data (see Figure 15) in the external data memory.
External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator
clock period in standard mode or 6 oscillator clock periods in X2 mode. For further infor-
mation on X2 mode.
Slow peripherals can be accessed by stretching the read and write cycles. This is done
using the M0 bit in AUXR register. Setting this bit changes the width of the RD and WR
signals from 3 to 15 CPU clock periods.
For simplicity, the accompanying figures depict the bus cycle waveforms in idealized
form and do not provide precise timing information. For bus cycle timing parameters
refer to the Section “AC Characteristics”.
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