Registers
Table 18. PSW Register
PSW (S:D0h)
Program Status Word Register
7
6
5
4
3
2
1
0
CY
AC
F0
RS1
RS0
OV
F1
P
Bit
Bit
Number Mnemonic Description
7
CY
Carry Flag
Carry out from bit 1 of ALU operands.
6
AC
Auxiliary Carry Flag
Carry out from bit 1 of addition operands.
5
F0
User Definable Flag 0.
4-3
RS1:0
Register Bank Select Bits
Refer to Table 16 for bits description.
2
OV
Overflow Flag
Overflow set by arithmetic operations.
1
F1
User Definable Flag 1
Parity Bit
0
P
Set when ACC contains an odd number of 1’s.
Cleared when ACC contains an even number of 1’s.
Reset Value = 0000 0000b
Table 19. AUXR Register
AUXR (S:8Eh)
Auxiliary Register
7
6
5
4
3
2
1
0
-
-
M0
-
XRS1
XRS0
EXTRAM
A0
Bit
Number
7-6
5
4
3-2
Bit
Mnemonic Description
-
Reserved
The value read from these bits are indeterminate. Do not set this bit.
Stretch MOVX control:
the RD/ and the WR/ pulse length is increased according to the value of M0.
M0 M0 Pulse length in clock period
0
6
1
30
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
XRS1-0
XRAM size:
Accessible size of the XRAM
XRS 1:0 XRAM size
0 0 256 Bytes
0 1 512 Bytes
1 0 768 Bytes
1 1 1024 Bytes (default)
28 A/T89C51AC2
4127H–8051–02/08