T89C51RD2-DDSC-M View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'T89C51RD2-DDSC-M' PDF : 86 Pages View PDF
T89C51RD2
They are several software registers described in Table 29
Table 29. Default values
Mnemonic
Default value
BSB Boot Status Byte
FFh
SBV Software Boot Vector
FCh
HSB Copy of the Hardware security byte 18h or 1Bh
SSB Software Security Byte
FFh
Copy of the Manufacturer Code
58h
ATMEL Wireless and
Microcontrollers
Copy of the Device ID #1: Family Code D7h
Copy of the Device ID #2: memories
size and type
FCh
Copy of the Device ID # 3: name and revi-
sion
FFh
C51 X2, Electrically Erasable
T89C51RD2 memories size
T89C51RD2, revision 0
After programming the part by ISP, the BSB must be reset (00h) in order to allow the application to boot at 0000h.
The content of the Software Security Byte (SSB) is described in Table 30 and Table 31
To assure code protection from a parallel access, the HSB must also be at the required level.
Table 30. Software Security Byte (SSB)
7
6
5
4
3
2
1
0
-
-
-
LB1
-
-
-
LB0
Bit
Number
7
6
5
4
1-3
0
Bit
Mnemonic
-
Reserved
Do not clear this bit.
-
Reserved
Do not clear this bit.
-
Reserved
Do not clear this bit.
User Memory Lock Bit
LB1
See Table 31
-
Reserved
Do not clear this bit.
User Memory Lock Bit
LB0
See Table 31
Description
The three lock bits provide different levels of protection for the on-chip code and data, when programmed according
to Table 31.
Rev. F - 15 February, 2001
54
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