TC646B/TC648B/TC649B
+5V
R1
237 kΩ
R2
45.3kΩ
Thermometrics®
100 kΩ @25°C
NHQ104B425R5
CB
1 VIN
0.01 µF
8
VDD
+ CVDD
1.0 µF
FAULT 6
+5V
R3
32.4 kΩ
R4
17.8 kΩ
3 VAS
CB
0.01 µF
2 CF
CF
1.0 µF
TC649B VOUT 7
SENSE 5
GND
4
R5
10 kΩ
CSENSE
0.1 µF
+12V
Panasonic®
Fan 12V, 140 mA
FBA06T12H
Q1
SI2302
or
MGSF1N02E
RSENSE
3.0Ω
FIGURE 5-13:
Design Example Schematic.
Bypass capacitor CVDD is added to the design to
decouple the bias voltage. This is good to have, espe-
cially when using a MOSFET as the drive device. This
helps to give a localized low-impedance source for the
current required to charge the gate capacitance of Q1.
Two other bypass capacitors (labeled as CB) were also
added to decouple the VIN and VAS nodes. These were
added simply to remove any noise present that might
cause false triggerings or PWM jitter. R5 is the pull-up
resistor for the FAULT output. The value for this resistor
is system-dependent.
DS21755B-page 26
2003 Microchip Technology Inc.