TC7109 View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
'TC7109' PDF : 30 Pages View PDF
TC7109/A
4.2 Handshake Mode
The Handshake mode provides an interface to a wide
variety of external devices. The byte enables may be
used as byte identification flags, or as load enables,
and external latches may be clocked by the rising edge
of CE/LOAD. A handshake interface to Intel® micropro-
cessors using an 8255 PPI is shown in Figure . The
handshake operation with the 8255 is controlled by
inverting its Input Buffer Full (IBF) flag to drive the
SEND input to the TC7109A, and using the CE/LOAD
to drive the 8255 strobe. The internal control register of
the PPI should be set in MODE 1 for the port used. If
the 8255 IBF flag is LOW and the TC7109A is in Hand-
shake mode, the next word will be strobed into the port.
The strobe will cause IBF to go HIGH (SEND goes
LOW), which will keep the enabled byte outputs active.
The PPI will generate an interrupt which, when
executed, will result in the data being read. The IBF will
be reset LOW when the byte is read, causing the
TC7109A to sequence into the next byte. The MODE
input to the TC7109A is connected to the control line on
the PPI.
The data from every conversion will be sequenced in
two bytes in the system, if this output is left HIGH, or
tied HIGH separately. (The data access must take less
time than a conversion.) The output sequence can be
obtained on demand if this output is made to go from
LOW to HIGH and the interrupt may be used to reset
the MODE bit.
Conversions may be obtained on command under soft-
ware control by driving the RUN/HOLD input to the
TC7109A by a bit of the 8255. Another peripheral
device may be serviced by the unused port of the 8255.
The Handshake mode is particularly useful for directly
interfacing to industry standard UARTs (such as Intersil
HD-6402), providing a means of serially transmitting
converted data with minimum component count.
A typical UART connection is shown in Figure . In this
circuit, any word received by the UART causes the
UART DR (Data Ready) output to go HIGH. The MODE
input to the TC7109A goes HIGH, triggering the
TC7109A into Handshake mode. The high order byte is
output to the UART and when the UART has trans-
ferred the data to the Transmitter register, TBRE
(SEND) goes HIGH again, LBEN will go HIGH, driving
the UART DRR (Data Ready Reset), which will signal
the end of the transfer of data from the TC7109A to the
UART.
An extension of the typical connection to several
TC7109A’s with one UART is shown in Figure 4-7. In
this circuit, the word received by the UART (available at
the RBR outputs when DR is HIGH) is used to select
which converter will handshake with the UART. Up to
eight TC7109A’s may interface with one UART, with no
external components. Up to 256 converters may be
accessed on one serial line with additional
components.
15 Q3 CD4060B
RESET
11
+5V 1 V
TRC 40
RRC 17
GND 3 GND
EPE 39 +5V
+5V 4 RRD
CLS1 38
CLS2 37
5–12 RBR1–8
SBS 36
HD-640R
PI 35 GND
13 PE CMOS UART CRL 34 +5V
14 FE
15 OE
*TBR1–8 26–33
8
GND 16 SFD
TRE 24
20 RR1
DRR 18
DR 19
Serial
Input
TBRL 23
TBRE 22
25 TRO
MR 21 GND
Serial
Output
CLK
10
V+ 40 +5V
GND 1 GND
REF IN- 39
–
25 BUFF OSC OUT REF CAP- 38
2 STATUS
REF CAP+ 37
1μF
External
Reference
19 HBEN
REF IN+ 36
IN HI 35
IN LO 34
1MΩ
0.01μF
+
+
Input
–
TC7109A COM 33
Analog GND
6 3–8 B9 - B12,
POL, OR
8 9–16 B1 - B8
INT 32
AZ 31
BUFF 30
CINT
CAZ 0.15μF
0.33μF
17 TEST
18 LBEN
REF OUT
V-
29
28
RINT 20kΩ
100kΩ
-5V
0.2VREF
1VREF
21 MODE
RUN/HOLD 26 +5V or Open
20 CE/LOAD
OSC SEL 24 GND
27 SEND
OSC OUT 23
OSC IN 22
3.58MHz
Crystal
*Note: For lowest power consumption, TBR1-TBR8 inputs should have 100kΩ pull-up resistors to +5V.
Send any word to UART to transmit latest result.
FIGURE 4-6:
TC7109 Typical UART Interface
DS21456C-page 20
© 2006 Microchip Technology Inc.
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