TCS3413 View Datasheet(PDF) - austriamicrosystems AG
Part Name
Description
MFG CO.
'TCS3413' PDF : 56 Pages View PDF
TCS3404, TCS3414 − Principles of Operation
Figure 43:
ADC Channel Data Registers
ADC Channel Data Registers (10h - 17h)
The ADC channel data are expressed as 16-bit values spread
across four registers. The channel low and high provide the
lower and upper bytes respectively for each ADC channel data
registers. Each DATALOW and DATAHIGH register is identified
below as 1, 2, 3, or 4. All channel data registers are read-only
and default to 00h on power up.
Register
GREEN_LOW
GREEN_HIGH
RED_LOW
RED_HIGH
BLUE_LOW
BLUE_HIGH
CLEAR_LOW
CLEAR_HIGH
Address
10h
11h
12h
13h
14h
15h
16h
17h
Bits
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
Description
ADC channel 1 lower byte
ADC channel 1 upper byte
ADC channel 2 lower byte
ADC channel 2 upper byte
ADC channel 3 lower byte
ADC channel 3 upper byte
ADC channel 4 lower byte
ADC channel 4 upper byte
The upper byte data registers can only be read following a read
to the corresponding lower byte register. When the lower byte
register is read the upper eight bits are strobed into a shadow
register, which is read by a subsequent read to the upper byte.
The upper register will therefore read the correct value even if
additional ADC integration cycles complete between the
reading of the lower and upper registers.
Note(s): The SMBus Read Word protocol can be used to read
byte-paired registers. For example, the DATA1LOW and
DATA1HIGH registers (as well as the other three individual
register pairs) may be read together to obtain the 16-bit ADC
value in a single transaction.
Page 32
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[v1-00] 2015-Nov-11
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