TCS3415 View Datasheet(PDF) - austriamicrosystems AG
Part Name
Description
MFG CO.
'TCS3415' PDF : 56 Pages View PDF
Figure 37:
Timing Register
7
Resv
6
SYNC_EDGE
TCS3404, TCS3414 − Principles of Operation
Timing Register (01h)
The Timing Register controls the synchronization and
integration time of the ADC channels. The Timing Register
settings apply to all four ADC channels. The Timing Register
defaults to 00h at power On.
5
4
3
2
1
0
INTEG_MODE
PARAM
Field
Resv
SYNC_EDGE
INTEG_MODE
Bits
7
6
5:4
Description
Reserved. Write as 0.
Sync pin edge. If SYNC_EDGE is low, the falling edge of the sync pin is used to stop
an integration cycle when INTEG_MODE is 11. If SYNC_EDGE is high, the rising
edge of the sync pin is used to stop an integration cycle when INTEG_MODE is 11.
Selects preset integration time, manual integration (via serial bus), or external
synchronization (SYNC IN) modes.
Field Value
Mode
In this mode, the integrator is free-running and one of
00
the three internally-generated Nominal Integration
Times is selected for each conversion
(see Integration Time table below).
01
Manually start/stop integration through serial bus using
ADC_EN field in Control Register.
Synchronize exactly one internally-timed integration
10
cycle as specified in the NOMINAL INTEGRATION TIME
beginning 2.4μs after being initiated by the SYNC IN pin.
Integrate over specified number of pulses on SYNC IN
11
pin (See SYNC IN PULSE COUNT table below). Minimum
width of sync pulse is 50μs. SYNC IN must be low at least
3.6μs.
Page 24
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ams Datasheet
[v1-00] 2015-Nov-11
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