Stereo decoder part
Figure 24. Vn timing diagram
V in
V
op
DC
TDA7402
TR
T HIGH
TF
Tim e
Figure 25. Trigger threshold vs. VPEAK
VTH
uct(s) 260mV (00)
d 220mV (01)
ro 180mV (10)
140mV (11)
te P MIN. TRIG. THRESHOLD
le 8 STEPS
65m V
30m V
so 0.9V
N O ISE C O N TR OLLE D TRIG . TH R ES HO LD
1.5V
VPEAK [V]
Ob Figure 26. Deviation controlled trigger adjustment
- VPEAK
t(s) [VOP]
c 00
du2.8
ro 01
2 .0
P 10
te 1.2
0 .9
D etector off (11)
ole 20
32.5
45
75
D EVIATION [KH z]
Obs Figure 27. Field strength controlled trigger adjustment
VPEAK
MONO
STEREO
» 3V
NOISE
noisy signal
2.3V (00)
1.8V (01)
1.3V (10)
ATC_SB OFF (11)
good signal
0.9V
E'
36/69