TDA7502 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'TDA7502' PDF : 25 Pages View PDF
I2C timing
5
I2C timing
TDA7502
Figure 15. Definition of timing for the I2C bus.
SDA
tBUF
tLOW
tSU:STA
tF
SCL
tHD:STA
tR
tHD:DAT
tHIGH
tSU:DAT
tHD:STA
tSU:STO
D02AU1371
Table 14. Definitions
Symbol
Parameter
Test condition
Standard
mode
I2C bus
Fast mode
I2C bus
Unit
FSCL
tBUF
SCLl clock frequency
Bus free between a STOP and Start
Condition
Hold time (repeated) START condition.
tHD:STA After this period, the first clock pulse is
generated
tLOW LOW period of the SCL clock
tHIGH HIGH period of the SCL clock
tSU:STA Set-up time for a repeated start condition
tHD:DAT DATA hold time
tR Rise time of both SDA and SCL signals Cb in pF
tF Fall time of both SDA and SCL signals Cb in pF
tSU;STO Set-up time for STOP condition
tSU:DAT Data set-up time
Cb Capacitive load for each bus line
Min. Max.
0 100
4.7
–
Min.
0
1.3
Max.
400 kHz
–
μs
4.0
–
0.6
–
μs
4.7
–
1.3
–
μs
4.0
–
0.6
–
μs
4.7
–
0.6
–
μs
0
–
0
0.9 μs
– 1000 20+0.1Cb 300 ns
–
300 20+0.1Cb 300
ns
4
–
0.6
–
μs
250 --
--
100 ns
– 400
–
400 pF
16/25
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