TDA7505 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'TDA7505' PDF : 38 Pages View PDF
TDA7505
Functional description
5.2.14
Clock scheme
Due to the programmable PLL oscillator, the clock scheme is very flexible. The customer
may choose the clock frequency according to the application needs. However one should
take into account several constraints:
● The RDS module needs a crystal frequency of 8.55 MHz or alternative an external
74.1MHz Oscillator. However the PLL may be supplied by an external clock reference
and the crystal in parallel may drive the RDS module.
● The CODEC (A/D and D/A) module needs a clock of 512 times the audio sample rate
(Fs).
● The audio sample rate (Fs) should be close to 44.1 kHz. This allows CD quality. Higher
sample rates will reduce the number of DSP clock cycles per Fs and hence will reduce
the available MIPS.
● The DSP core clock frequency may not exceed 76 MHz
● In a car radio system the second and third system clock harmonics (DSP clock and
CODEC clock) should be outside the radio frequency bands.
Two examples of convenient clock schemes are shown in the following table:
Table 28. Examples of convenient clock schemes
Clock scheme
Fxtal
Fcomp
Fvco
Fdsp
Fcodec
Fs
8.55 MHz
Fxtal / 4
2.14 MHz
Fcomp * 106
226.58 MHz
Fvco / 3
75.53 MHz
Fvco / 10
22.66 MHz
44.25 kHz
1. External clock oscillator used
Alternative(1)
74.1 MHz
Fxtal/21
3.53 MHz
Fcomp * 64
225.8 MHz
Fvco / 3
75.28 MHz
Fvco / 10
22.58 MHz
44.11 kHz
33/38
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