TDA7580 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'TDA7580' PDF : 31 Pages View PDF
SAI Interface
3
SAI Interface
TDA7580
Note:
Figure 5. SAI Timings
SDI0-1
LRCKR
SCKR
(RCKP=0)
Valid
Valid
tlrs
tdt
tsdis
tsckpl
tlrh
tsdih
tsckph
tsckr
Table 17.
SAI Timing table
(Tj =-40°C to 125°C; VDD =1.7V to 1.9V, VDD3 = 3.15V to 3.45V) Cload The
values on the table are consistent with a capacitance load on SAI lines of
160pF
Timing
Description
Min Typ Max Unit
tsckr
tdt
tlrs
tlrh
tsdis
tsdih
tsckph
tsckpl
Clock Cycle
SCKR active edge to data out valid
LRCK setup time
LRCK hold time
SDI setup time
SDI hold time
SCK high time
SCK low time
302
976 ns
48
65
ns
25
ns
25
ns
65
ns
65
ns
146
ns
146
ns
TDSP = DSP master clock cycle time = 1/FDSP
Figure 6. SAI protocol (when: RLRS=0; RREL=0; RCKP=1; RDIR=0)
LRCKR
SCKR
LEFT
RIGHT
SDI0-1
LSB(n-1)
MSB(n)
MSB-1(n)
MSB-2(n)
20/39
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