TDA7719
I2C bus specification
Table 27. Testing audio processor 2 (20)
MSB
D7
D6
D5
D4
D3
D2
0
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
x
x
x
1. The control bit needs sub-address test mode on
2. The control bit does not depend on test mode.
LSB
D1
D0
Function
Test Architecture (1)
0 normal
1 Split
Oscillator Clock (2)
0
400kHz
1
800kHz
Softstep Curve (2)
S-Curve
Linear Curve
Manual Set Busy Signal (1)
Auto
Auto
0
1
Request for Clk Generator (1)
Allow
Allow
Stopped
Stopped
Not Used
Doc ID 13698 Rev 5
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