TDA8007B View Datasheet(PDF) - Philips Electronics
Part Name
Description
MFG CO.
'TDA8007B' PDF : 36 Pages View PDF
Philips Semiconductors
Double multiprotocol IC card interface
Product specification
TDA8007B
Error management in protocol:
• T = 0:
In the event of a parity error, the received byte is not
stored in the FIFO, and the error counter is incremented.
The error counter is programmable between 1 and 8.
When the programmed number is reached, bit PE is set
in the status register USR and INT goes LOW. The error
counter must be reprogrammed to the desired value after
its count has been reached.
• T = 1:
In the event of a parity error, the character is loaded in the
FIFO, and bit PE is set whatever the programmed value
in parity error counter.
When the FIFO is full, bit RBF in the status register USR
is set. This bit is reset when at least one character has
been read from the URR.
When the FIFO is empty, bit FE is set as long as no
character has been received.
The Mixed Status Register (see Table 10) relates the
status of pin INTAUX, the cards presence contacts PR1
and PR2, the BGT counter, the FIFO empty indication
and the transmit/receive ready indicator TBE/RBF.
Bit INTAUX is set when the level on pin INTAUX is HIGH,
it is reset when the level is LOW.
Bit BGT is linked with a 22 ETU counter, which is started
at every start bit on the I/O. Bit BGT is set if the count is
finished before the next start bit. This helps to verify that
the card has not answered before 22 ETUs after the last
transmitted character, or not transmitting a character
before 22 ETUs after the last received character.
PR1 is HIGH when card 1 is present, PR2 is HIGH when
card 2 is present.
FE is set when the reception FIFO is empty. It is reset
when at least one character has been loaded in the FIFO.
Bit TBE/RBF (Transmit Buffer Empty/Receive Buffer Full)
is set when:
• Changing from reception mode to transmission mode
• A character has been transmitted by the UART
• The reception FIFO is full.
Bit TBE/RBF is reset after Power-on or after one of the
following:
• When bit RIU is reset
• When a character has been written to the UTR
• When at least one character has been read in the FIFO
• When changing from transmission mode to reception
mode.
No bits within the MSR act upon INT:
• The FIFO Control Register bits are given in Table 11,
FL2, FL1 and FL0 determine the depth of the FIFO
(000 = length 1, 111 = length 8).
PEC2, PEC1 and PEC0 determine the number of parity
errors before setting bit PE in the USR and pulling
INT LOW; 000 indicates that if only one parity error has
occurred, bit PE is set; 111 indicates that bit PE will be set
after 8 parity errors.
PEC2, PEC1 and PEC0 need to be reprogrammed to the
desired value after bit PE has been set.
In protocol T = 0:
• If a correct character is received before the
programmed error number is reached the error counter
will be reset.
• If the programmed number of allowed parity errors is
reached, bit PE in the USR will be set as long as the
USR has not been read.
In protocol T = 1:
• The error counter has no action (bit PE is set at the first
wrong received character).
• The UART Status Register (see Table 12) is used by
the microcontroller to monitor the activity of the
ISO UART and that of the time-out counter.
Transmission Buffer Empty (TBE) is HIGH when the
UART is in transmission mode, and when the
microcontroller may write the next character to transmit in
the UTR. It is reset when the microcontroller has written
data in the transmit register or when bit T/R within UCR1
has been reset either automatically or by software.
After detection of a parity error in transmission, it is
necessary to wait 13 ETUs before rewriting the character
which has been Not ACKnowledged (NAK) by the card.
Reception Buffer Full (RBF) is HIGH when the FIFO is full.
The microcontroller may read some of the characters in
the URR, which clears bit RBF.
TBE and RBF share the same bit within the USR (when in
transmission mode, the relevant bit is TBE; when in
reception mode, it is RBF).
Framing Error (FER) is HIGH when the I/O was not in the
high-impedance state at 10.25 ETUs after a start bit. It is
reset when the USR has been read-out.
2000 Nov 09
14
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