TDA9106 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'TDA9106' PDF : 30 Pages View PDF
TDA9106
HORIZONTAL SECTION (continued)
Electrical Characteristics (VCC = 12V, Tamb = 25oC) (continued)
Symbol
Parameter
Test Conditions
Min. Typ. Max. Unit
1st PLL SECTION
HpolT Polarity Integration Delay
VVCO VCO Control Voltage (Pin12)
Vcog VCO Gain (Pin 12)
Hph
Hphmin
Hphtyp
Hphmax
f0
Horizontal Phase Adjustment
Horizontal Phase Decoupling Output
Minimum Value
Typical Value
Maximum Value
Free Running Frequency
dF0/dT Free Running Frequency Thermal Drift
(No drift on external components)
VREF-H = 8V
f0
fH(Max.)
R0 = 6.49kΩ, C0 = 820pF,
dF/dV = 1/11R0C0
% of Horizontal Period
Sub-Address 01, Pin 14
Byte x1111111
Byte x1000000
Byte x0000000
R0 = 6.49kΩ, C0 = 820pF,
f0 = 0.97/8R0C0
0.75
VREF-H / 6
6.2
17
±10
2.8
3.4
4.0
22.3
-150
ms
V
V
kHz/V
%
V
V
V
kHz
ppm/C
f0(Min.)
f0(Max.)
CR
Free Running Frequency Adjustment
Minimum Value
Maximum Value
PLL1 Capture Range
Sub-Address 02
Byte xxx11111
Byte xxx00000
0.8
F0
1.3
F0
R0 = 6.49kΩ, C0 = 820pF,
from f0+0.5kHz to 4.5F0
fH(Min.)
fH(Max.)
100
23.5 kHz
kHz
PLLinh PLL1 Inhibition (Pin3)
Typ Threshold = 1.6V
PLL ON
PLL OFF
2
0.8
V
V
SFF Safe Forced Frequency
Sub-Address 02
SF1 Byte 11xxxxxx
2F0
SF2 Byte 10xxxxxx
3F0
VCO Sawtooth Level
FC1
FC2
High FC1=(4.VREF-H)/5
Low FC2=(VREF-H)/5
Pin 9 To filter
Pin 8 To filter
6.4
V
1.6
V
2nd PLL SECTION AND HORIZONTAL OUTPUT SECTION
FBth
Hjit
HDmin
HDmax
XRAYth
Vphi2
VSCinh
IHblk
VHblk
Flyback Input Threshold Voltage (Pin 6)
Horizontal Jitter (see Pins 8-9 filtering)
Horizontal Drive Output Duty-Cycle
(Pin 20 or 21) (see Note 1)
Low Level
High Level (see Note 2)
X-RAY Protection Input Threshold Voltage
Internal Clamping Levels on 2nd PLL Loop
Filter (Pin 4)
Threshold Voltage To Stop H-Out,V-Out
when VCC < VSCinh
Maximum Horizontal Blanking Output
Current
Horizontal Blanking Output Low Level
(Blanking ON)
Sub-Address 00
Byte xxx11111
Byte xxx00000
Pin 15
Low Level
High Level
Pin 18
I22
V22 with I22 = 10mA
0.65 0.75
V
TBD
ppm
30
%
60
%
8
V
1.6
V
4.0
V
7.5
V
10 mA
0.25 0.5
V
HDvd
HDem
Horizontal Drive Output
Low Level (Pin 20 to GND)
High Level (Pin 21 to VCC=12V)
V21-V20, IOUT = 20mA
V20, IOUT = 20mA
1.1 1.7
V
9.5
10
V
Notes : 1. Duty Cycle is the ratio of power transistor OFF time to period. Power transistor is OFF when output transistor is OFF.
2. Initial Condition for Safe Operation Start Up (Max. duty cycle).
7/30
Share Link: 
