TDA9109/N View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'TDA9109/N' PDF : 32 Pages View PDF
TDA9109/N
OPERATING DESCRIPTION (continued)
The sync frequencymust always be higherthan the
free running frequency. For example, when using a
sync range between 24kHz and 100kHz, the sug-
gested free running frequency is 23kHz.
This can be obtained only by adjusting f0 (for in-
stance, making R0 adjustable). If no adjustment is
possible, more margin must be provided to cope
with the componentsspread : ±8% for the IC, ±1%
for R0, ±2 or 5% for C0, leading to ±11% or 14% on
f0. The same percentage of frequency range will
lost at upper end of the range.
Another feature is the capability for the MCU to
force the horizontal frequency through I2C to 2xf0
or 3xf0 (for burn-in mode or safety requirements).
In this case, the inhibition switch is opened, leaving
PLL1 free, but the voltage on PLL1 filter is forced
to 2.66V (for 2xf0) or 4.0V (for 3xf0).
PLL1 ensuresthe coincidencebetween the leading
edge of the sync signal and a phase reference
obtained by comparison between the sawtooth of
the VCO and an internal DC voltage which is I2C
adjustable between 2.8V and 4.0V (corresponding
to ± 10%) (see Figure 10).
Figure 10 : PLL1 Timing Diagram
H Osc
Sawtooth 7/8TH
1/8TH
Phase REF1
6.4V
2.8V < Vb < 4.0V
Vb
1.6V
H Synchro
Phase REF1 is obtained by comparison between the sawtooth and
a DC voltage adjustable between 2.8V and 4.0V. The PLL1 en-
sures the exact coincidence between the signal phase REF and
HSYNC. A ± TH/10 phase adjustment is possible.
The TDA9109/N also includes a Lock/Unlock iden-
tification block which senses in real time whether
PLL1 is locked or not on the incoming horizontal
sync signal. The resulting information is available
on HLOCKOUT (see Sync Processor).
When PLL1 is unlocked, it forces HLOCKOUT to
high level.
The lock/unlock information is also available
through the I2C read.
II.3 - PLL2
PLL2 ensures a constant position of the shaped
flyback signal in comparison with the sawtooth of
the VCO, taking into accountthe saturationtime Ts
(see Figure 11).
Figure 11 : PLL2 Timing Diagram
H Osc
Sawtooth 7/8TH
1/8TH
6.4V
4.0V
1.6V
Flyback
Internally
Shaped Flyback
H Drive
Ts
Duty Cycle
The duty cycle of H-drive is fixed (48%).
The phase comparator of PLL2 (phase type com-
parator) is followed by a charge pump (typical
output current : 0.5mA).
The flyback input consists of an NPN transistor.
This input must be current driven. The maximum
recommendedinput current is 5mA(see Figure 12).
The duty cycle is fixed (48%).
The maximum storage time (Ts Max.) is (0.44TH -
TFLY/2). Typically, TFLY/TH is around 20% which
means that Ts max is around 34% of TH.
Figure 12 : Flyback Input Electrical Diagram
HFLY 12
400Ω
Q1
20kΩ
GND 0V
19/32
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