TDA9109/N View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'TDA9109/N' PDF : 32 Pages View PDF
TDA9109/N
OPERATING DESCRIPTION (continued)
Figure 16 : AGC Loop Block Diagram
VSYNCIN 2
SYNCHRO
POLARITY
DISCH.
OSCILLATOR
CHARGE CURRENT
TRANSCONDUCTANCE
AMPLIFIER
22
OSC
CAP
REF
20
SAMPLING
SAMPLING
CAPACITANCE
Vlow
Sawth.
Disch.
VERT_AMP
SUB05/7bits
VMOIRE
SUB0C/5bits
VPOSITION
SUB06/7bits
S CORRECTION
VS_AMP
SUB07/6bits
COR_C
SUB08/6bits
C CORRECTION
18 BREATH
23 VOUT
III.4 - Basic Equations
In first approximation,the amplitude of the ramp on
Pin 23 (VOUT) is :
VOUT - VPOS = (VOSC - VDCMID) ⋅ (1 + 0.25 (VAMP))
with :
- VDCMID = 7/16 ⋅ VREF (middle value of the ramp
on Pin 22, typically 3.5V)
- VOSC = V22 (ramp with fixed amplitude)
- VAMP = -1 for minimum vertical amplitude register
value and +1 for maximum
- VPOS is calculated by : VPOS = VDCMID + 0.3 VP
with VP equals -1 for minimum vertical position
register value and +1 for maximum
The current available on Pin 22 is :
IOSC
=
3
8
⋅
VREF
⋅
COSC
⋅
f
with : COSC : capacitor connected on Pin 22 and
f : synchronization frequency.
III.5 - Geometric Corrections
The principle is represented in Figure 17.
Starting from the vertical ramp, a parabola-shaped
current is generatedfor E/W correction (also known
as Pin Cushion correction), dynamic horizontal
phase control correction, and vertical dynamic Fo-
cus correction.
The parabola generator is made by an analog
multiplier, the output current of which is equal to :
DI = k ⋅ (VOUT - VDCMID)2
where VOUT is the vertical output ramp (typi-
cally between 2 and 5V) and VDCMID is 3.5V (for
VREF-V = 8V).
The VOUT sawtooth is typically centered on 3.5V.
By changing the vertical position, the sawtooth
shifts by ±0.3V.
In order to have good screen geometry for any end
user adjustment, the TDA9109/N has the ”geome-
try tracking” feature, which allows generation of a
dissymetric parabola depending on the vertical
position.
Due to the large output stage voltage range (E/W,
Keystone), the combination of tracking function
with maximum vertical amplitude, maximum or
minimum vertical position and maximum gain on
the DAC control may lead to the output stage
saturation. This must be avoided by limiting the
output voltage with apropriate I2C registers values.
22/32
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