TDA9109/S View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'TDA9109/S' PDF : 30 Pages View PDF
TDA9109/S
OPERATING DESCRIPTION (continued)
II.2 - PLL1
The PLL1 consists of a phase comparator, an exter-
nal filter and a voltage-controlled oscillator (VCO).
The phase comparator is a "phase frequency" type
designed in CMOS technology. This kind of phase
detector avoids locking on wrong frequencies. It is
followed by a "charge pump", composed of two
current sources : sunk and sourced (typically I = 1mA
when locked and I = 140µA when unlocked). This
difference between lock/unlock allows smooth catch-
ing of the horizontal frequency by PLL1. This effect
is reinforced by an internal original slow down system
when PLL1 is locked, avoiding the horizontal fre-
quency changing too quickly.
The dynamic behaviour of PLL1 is fixed by an exter-
nal filter which integrates the current of the charge
pump. A "CRC" filter is generally used (see Figure 7).
The PLL1 is internally inhibited during extracted
vertical sync (if any) to avoid taking in account
missing pulses or wrong pulses on phase compara-
tor.The inhibition is done by a switch located be-
tween the charge pump and the filter (see Figure 8).
The VCO uses an external RC network. It delivers
a linear sawtooth obtained by the charge and the
discharge of the capacitor, with a current propor-
tional to the current in the resistor. The typical
Figure 8 : Block Diagram
H/HVIN 1
INPUT
INTERFACE
Tramext
LOCKDET
COMP1
E2
High
Low
Figure 7
PLL1F
7
1.8kW
1m F
4.7m F
thresholds of the sawtooth are 1.6V and 6.4V.
The control voltage of the VCO is between 1.33V
and 6V (see Figure 9). The theorical frequency
range of this VCO is in the ratio of 1 to 4.5. The
effective frequency range has to be smaller (1 to
4.2) due to clamp intervention on the filter lowest
value. To remove the device and external compo-
nents spread, it is possible to adjust the free run-
ning frequency through I2C. This adjustment can
be done automatically on the manufacturing line
without manual operation by using Hlock/unlock
information. The adjustment range is 0.8 to 1.3 f0
(where 1.3 f0 is the free running frequency at power
on reset).
Lock/Unlock
PLL1F R0 C0
Status
Tramext
I2C
7
65
Forced
Frequency
CHARGE
PUMP
PLL
INHIBITION
HPOSITION
8
PHASE
ADJUST
VCO
I2C
HPOS
Adj.
OSC
Figure 9 : Details of VCO
PLL1F
(Loop Filter)
7
(1.3V < V7 < 6V)
I2C Free Running
Adjustment
I0
2
a
I0
(0.80 < a < 1.30)
4 I0
6
R0
6.4V
1.6V
RS
FLIP FLOP
5
6.4V
C0
1.6V
0 0.875TH TH
18/30
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