TDA9109N View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'TDA9109N' PDF : 32 Pages View PDF
TDA9109/N
OPERATING DESCRIPTION (continued)
Figure 15
Horizontal Flyback
Internal Trigged
Horizontal Flyback
Horizontal Focus
Cap Sawtooth
Horizontal Dynamic
Focus Parabola
Output
400ns
4.7V
2V
2V
III - VERTICAL PART
III.1 - Function
When the synchronization pulse is not present, an
internal current source sets the free running fre-
quency. For an external capacitor, COSC = 150nF,
the typical free running frequency is 100Hz.
The typical free running frequency can be calcu-
lated by :
f0
(Hz)
=
1.5
⋅
10−5
⋅
1
COSC
A negative or positive TTL level pulse applied on
Pin 2 (VSYNC)as well as a TTLcomposite sync on
Pin 1 can synchronize the ramp in the range
[fmin , fmax]. This frequencyrange depends on the
external capacitor connected on Pin 22.
A 150nF (±5%) capacitor is recommended for
50Hz to 165Hz applications.
The typical maximum and minimum frequency, at
25oC and without any correction (S correction or
C correction), can be calculated by :
f(Max.) = 2.5 x f0 and f(Min.) = 0.33 x f0
If S or C corrections are applied, these values are
slighty affected.
If a synchronization pulse is applied, the internal
oscillator is synchonized immediately but its am-
plitude changes. An internal correction then ad-
justs it in less than half a second. The top value of
the ramp (Pin 22)is sampled on the AGC capacitor
(Pin 20) at each clock pulse and a transconduc-
tance amplifier modifies the charge current of the
capacitor in such a way to make the amplitude
again constant.
The read status register provides the vertical Lock-
Unlock and the vertical sync polarity information.
We recommend the use of an AGC capacitor with
low leakage current. A value lower than 100nA is
mandatory.
A good stability of the internal closed loop is
reached by a 470nF ± 5% capacitor value on
Pin 20 (VAGC).
III.2 - I2C Control Adjustments
S and C correction shapes can then be added
to this ramp. These frequency independent S
and C corrections are generated internally.
Their amplitudes are adjustable by their respec-
tive I2C registers. They can also be inhibited by
their select bits.
Finally, the amplitude of this S and C corrected
ramp can be adjusted by the vertical ramp ampli-
tude control register.
The adjusted ramp is available on Pin 23 (VOUT) to
drive an external power stage.
The gain of this stage can be adjusted (±25%)
depending on its register value.
The mean value of this ramp is driven by its own
I2C register (vertical position). Its value is
VPOS = 7/16 ⋅ VREF-V ± 300mV.
Usually VOUT is sent through a resistive divider to
the inverting input of the booster. Since VPOS
derives from VREF-V, the bias voltage sent to the
non-inverting input of the booster should also de-
rive from VREF-V to optimize the accuracy (see Ap-
plication Diagram).
III.3 - Vertical Moiré
By using the vertical moiré, VPOS can be modu-
lated from frame to frame. This function is intended
to cancel the fringes which appearwhen line to line
interval is very close to the CRT vertical pitch.
The amplitude of the modulation is controlled by
register VMOIRE on sub-address 0C and can be
switched-off via the control bit D7.
21/32
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