TDA9115 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'TDA9115' PDF : 45 Pages View PDF
TDA9115
9.8.4 Composite output HLckVBk
The composite output HLckVBk provides, at the
same time, information about lock state of PLL1
and early vertical blanking pulse. As both signals
have two logical levels, a four level signal is used
to define the combination of the two. Schematic di-
agram putting together all safety functions and
composite PLL1 lock and V-blanking indication is
in Figure 15, the combinations, their respective
levels and the HLckVBk configuration in Figure 16.
The early vertical blanking pulse is obtained by a
logic combination of vertical synchronization pulse
and pulse corresponding to vertical oscillator dis-
charge. The combination corresponds to the draw-
ing in Figure 16. The blanking pulse is started with
Figure 16. Levels on HLckVBk composite output
the leading edge of any of the two signals, which-
ever comes first. The blanking pulse is ended with
the trailing edge of vertical oscillator discharge
pulse. The device has no information about the
vertical retrace time. Therefore, it does not cover,
by the blanking pulse, the whole vertical retrace
period. By means of BlankMode I2C bus bit, when
at 1 (default), the blanking level (one of two ac-
cording to PLL1 status) is made available on the
HLckVBk permanently. The permanent blanking,
irrespective of the BlankMode I2C bus bit, is also
provided if the supply voltage is low (under VCCEn
or VCCDis thresholds), if the X-ray protection is ac-
tive or if the V-drive signal is disabled by VOutEn
I2C bus bit.
VCC
L1 - No blank/blank level
L2 - H-lock/unlock level
3 HLckVBk
ISinkLckBlk
L1(L)+L2(H)
L1(H)+L2(H)
VOLckBlk
L1(L)+L2(L)
L1(H)+L2(L)
V-early blanking
No
HPLL1 locked
Yes
Yes
No
Yes
Yes
No
No
35/45
Share Link: 
