TDA9964 View Datasheet(PDF) - Philips Electronics
Part Name
Description
MFG CO.
'TDA9964' PDF : 24 Pages View PDF
Philips Semiconductors
12-bit, 3.0 V, 30 Msps analog-to-digital
interface for CCD cameras
Objective specification
TDA9964
SYMBOL
PARAMETER
CONDITIONS
MIN.
Digital inputs
PINS: SHP, SHD AND CLK (REFERENCED TO DGND)
VIL
LOW-level input voltage
0
VIH
HIGH-level input voltage
2.2
Ii
input current
0 ≤ Vi ≤ 5.5 V
−3
Zi
input impedance
fCLK = 30 MHz
−
Ci
input capacitance
fCLK = 30 MHz
−
PINS: CLPDM, CLPOB, SEN, SCLK, SDATA, STBY, OE, BLK, VSYNC
VIL
LOW-level input voltage
0
VIH
HIGH-level input voltage
2.2
Ii
input current
0 ≤ Vi ≤ 5.5 V
−2
Clamps
GLOBAL CHARACTERISTICS OF THE CLAMP LOOPS
tW(clamp)
clamp active pulse width in PGA code = 255 for
12
number of pixels
maximum 4 LSB error
INPUT CLAMP (DRIVEN BY CLPDM)
gm(CDS)
CDS input clamp
−
transconductance
Correlated Double Sampling (CDS)
Vi(CDS)(p-p)
Vreset(max)
Ii(IN)
Ci
tCDS(min)
th(IN;SHP)
th(IN;SHD)
maximum peak-to-peak CDS VCC = 2.85 V
650
input amplitude (video signal) VCC ≥ 3.0 V
800
maximum CDS input reset
500
pulse amplitude
input current into pin IN
at floating gate level
tbf
input capacitance
−
CDS control pulses minimum
active time
CDS input hold time (pin IN)
compared to control pulse
SHP
Vi(CDS)(p-p) = 800 mV
−
black to white transition in
1 pixel with 99% Vi recovery
VCCA = VCCD = 3.0 V;
−
Tamb = 25 °C;
see Figs 3 and 4
CDS input hold time (pin IN) VCCA = VCCD = 3.0 V;
−
compared to control pulse Tamb = 25 °C;
SHD
see Figs 3 and 4
Amplifier
DRPGA
∆GPGA
PGA dynamic range
PGA gain step
Analog-to-Digital Converter (ADC)
DNL
differential non linearity
−
0.08
fpix = 30 MHz; ramp input −
TYP.
−
−
−
50
−
−
−
−
−
20
−
−
−
−
2
8
1
1
24
0.10
±0.5
MAX. UNIT
0.6 V
5.5 V
+3 µA
−
kΩ
2
pF
0.6 V
5.5 V
+2 µA
−
pixels
−
mS
−
mV
−
mV
−
mV
tbf µA
−
pF
−
ns
2
ns
2
ns
−
dB
0.12 dB
±0.9 LSB
2000 May 02
7
Share Link: 
