TMB2193MS100 View Datasheet(PDF) - Fairchild Semiconductor
Part Name
Description
MFG CO.
'TMB2193MS100' PDF : 24 Pages View PDF
TMB2193MS100
Input Edge Connector Design Notes
Signal Flow FORWARD
PRODUCT SPECIFICATION
Y/Composite
LPF and
Clamp Circuit
Chrominance
BPF and
Clamp Circuit
TMC2242
10 bit
ADCs
Digital
LPFs
TMC2242
SW1
SW2
11
EPROM
FPGA
32 32
Decoder
Input Logic
DC Supply
11
TMC2072
TMC22153
TMC3003
SW1
32 32
+5V 0V -5V
Signal Flow BACKWARD
Low Quality
LPF
Low Quality
LPF
Low Quality
LPF
65-B2193-14
1. Boards with different revision letters may not be
compatible. Damage may occur if they are con-
nected together!
2. XPXCK is a two times pixel clock fed BACKWARD.
3. XHSYNC and XVSYNC are timing reference signals
fed BACKWARD.
4. The MASTER/SLAVE signal states if a board is a
MASTER or a SLAVE board. This signal is fed
FORWARD. A MASTER board produces the PXCK,
HSYNC, and VSYNC signals, and a SLAVE board
expects to receive XPXCK, XHSYNC, XVSYNC, etc.
5. XDIR is fed FORWARD and controls in which direction
the XRS[3:0] data flows.
6. PGM_IN is a negative going pulse, logically ANDed
with the onboard program start pulse, for initiating the
programming sequence for components on that board.
Care must be taken to ensure that multiple devices do
not try to drive the RBUS at any given time. Minimum
width of PGM_IN is 1uS.
7. The RESET pin on the input edge connector should be
connected directly to the RESET pin on the output con-
nector. A link should be used to connect any pulse to the
RESET line.
8. The MASTER/SLAVE, XDIR, PGM_IN and RESET
pins on the input edge connector should be connected to
+5V through a 10k pull up resistor.
9. The CLAMP signal is fed BACKWARD from a
MASTER to a SLAVE board. The CLAMP signal
should not be fed FORWARD.
20
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