TSA1203IFT-E View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'TSA1203IFT-E' PDF : 30 Pages View PDF
TSA1203
8
Application information
Application information
The TSA1203 is a dual-channel, 12-bit resolution high speed analog-to-digital converter
based on a pipeline structure and deep sub-micron CMOS process to achieve the best
performance in terms of linearity and power consumption.
Each channel achieves 12-bit resolution through the pipeline structure which consists of 12
internal conversion stages in which the analog signal is fed and sequentially converted into
digital data. A latency time of 7 clock periods is necessary to obtain the digitized data on the
output bus.
The input signals are simultaneously sampled, for both channels, on the rising edge of the
clock. The output data is delivered on the rising edge of the clock for channel I, and on the
falling edge of the clock for channel Q, as shown in Figure 2: Timing diagram on page 4. The
digital data produced at the various stages must be time-delayed according to the order of
conversion. Finally, a digital data correction completes the processing and ensures the
validity of the ending codes on the output bus.
The TSA1203 is pin-to-pin compatible with the dual 10 bits/20 Msps TSA1005-20, the dual
10 bits /40 Msps TSA1005-40 and the dual 12 bits/ 20 Msps TSA1204.
8.1
8.1.1
8.1.2
Additional functions
To simplify the application board as much as possible, the following operating modes are
provided:
● Output enable (OEB) mode
● Select mode
Output enable mode (OEB)
When set to low level (VIL), all digital outputs remain active and are in low impedance state.
When set to high level (VIH), all digital output buffers are in high impedance state while the
converter goes on sampling. When OEB is set to a low level again, the data arrives on the
output with a very short Ton delay. This mechanism allows the chip select of the device.
Figure 2: Timing diagram on page 4 summarizes this functionality.
If you do not want to use OEB mode, the OEB pin should be grounded through a low value
resistor.
Select mode (SELECT)
The digital data output from each of the ADC cores is multiplexed to share the same output
bus. This prevents an increase in the number of pins and allows to use the same package as
for a single-channel ADC like the TSA1201.
The information channel is selected with the "SELECT" pin. When set to high level (VIH), the
channel I data is present on the D0-D11 output bus. When set to low level (VIL), the channel
Q data is delivered on D0-D11.
By connecting SELECT to CLK, channel I and channel Q are simultaneously present on D0-
D11, channel I on the rising edge of the clock and channel Q on the falling edge of the clock.
(refer to Figure 2: Timing diagram on page 4).
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