UPD703017AGC View Datasheet(PDF) - NEC => Renesas Technology
Part Name
Description
MFG CO.
'UPD703017AGC' PDF : 48 Pages View PDF
µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY
Bus Timing (CLKOUT Asynchronous)
(TA = –40 to +85°C, VDD = BVDD = 2.7 to 3.6 V, VSS = BVSS = 0 V, Output pin load capacitance: CL = 50 pF)
Parameter
Address setup time (to ASTB↓)
Address hold time (from ASTB↓)
Address float from DSTB↓
Data input setup time from address
Data input setup time from DSTB↓
Delay time from ASTB↓ to DSTB↓
Data input hold time (from DSTB↑)
Address output time from DSTB↑
Delay time from DSTB↑ to ASTB↑
Delay time from DSTB↑ to ASTB↓
DSTB low-level width
ASTB high-level width
Data output time from DSTB↓
Data output setup time (to DSTB↑)
Data output hold time (from DSTB↑)
WAIT setup time (to address)
WAIT hold time (from address)
WAIT setup time (to ASTB↓)
WAIT hold time (from ASTB↓)
HLDRQ high-level width
HLDAK low-level width
Bus output delay time from HLDAK↑
Delay time from HLDRQ↓ to HLDAK↓
Delay time from HLDRQ↑ to HLDAK↑
Symbol
tSAST
tHSTA
tFDA
tSAID
tSDID
tDSTD
tHDID
tDDA
tDDST1
<13>
<14>
<15>
<16>
<17>
<18>
<19>
<20>
<21>
tDDST2
tWDL
<22>
<23>
tWSTH
tDDOD
<24>
<25>
tSODD
tHDOD
<26>
<27>
tSAWT1
tSAWT2
<28>
<29>
tHAWT1
tHAWT2
<30>
<31>
tSSTWT1 <32>
tSSTWT2 <33>
tHSTWT1 <34>
tHSTWT2 <35>
tWHQH <36>
tWHAL <37>
tDHAC <38>
tDHQHA1 <39>
tDHQHA2 <40>
Conditions
n≥1
n≥1
n≥1
n≥1
n≥1
n≥1
n≥1
n≥1
MIN.
MAX.
Unit
0.5T – 15
ns
0.5T – 15
ns
2
ns
(2 + n)T – 25 ns
(1 + n)T – 25 ns
0.5T – 15
ns
0
ns
(1 + i)T – 15
ns
0.5T – 15
ns
(1.5 + i)T – 15
ns
(1 + n)T – 15
ns
T – 15
ns
15
ns
(1 + n)T – 20
ns
T – 15
ns
1.5T – 25
ns
(1.5 + n)T – 25 ns
(0.5 + n)T
ns
(1.5 + n)T
ns
T – 25
ns
(1 + n)T – 25 ns
nT
ns
(1 + n)T
ns
T + 10
ns
T – 15
ns
0
ns
(2n + 7.5)T + 25 ns
0.5T
1.5T + 25
ns
Remarks 1. T = 1/fCPU (fCPU: CPU operation clock frequency)
2. n: Number of wait clocks inserted in the bus cycle.
The sampling timing changes when a programmable wait is inserted.
3. i: Number of idle states inserted after the read cycle (0 or 1).
4. The values in the above specifications are values for when clocks with a 5:5 duty ratio are input from
X1.
Data Sheet U14526EJ2V0DS00
31
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