UPD72001C-11 View Datasheet(PDF) - NEC => Renesas Technology
Part Name
Description
MFG CO.
'UPD72001C-11' PDF : 40 Pages View PDF
µPD72001-11, 72001-A8
Serial control:
Parameter
Symbol
Condition
Transmit/receive data cycle
tCYD
STRXC, TRXC input clock cycle
tCYC
STRXC, TRXC input
tWCH
clock pulse width
tWCL
STRXC, TRXC↓ → delay time
tDTCTD1
tDTCTD2
TRXC↓ → TxD delay time
RXD setup time (vs. STRXC, TRXC ↑)
tDTCTD3
tSRDRC
RXD hold time (vs. STRXC, TRXC ↑)
tHRCRD
RXD → TXD delay time
TXD → INT delay time
TXD → DRQTX delay time
RxC ↑ Note → INT delay time
RxC ↑ Note → DRQRX delay time
RD ↓ → DRQRX ↓ delay time
WR ↓ → DRQTX ↓ delay time
tDRDTD1
tDRDTD2
tDTDIQ
tDTDDQ
tDRCIQ
tDRCDQ
tDRDQ
tDWDQ
TA = –10 to +70 °C
TA = –40 to +85 °C
High level
TA = –10 to +70 °C
TA = –40 to +85 °C
Low level
TA = –10 to +70 °C
TA = –40 to +85 °C
×1 mode, COP,
BOP
TA = –10 to +70 °C
TA = –40 to +85 °C
×16, 32, 64 mode TA = –10 to +70 °C
TA = –40 to +85 °C
TRXC is output
When DPLL is
not used
TA = –10 to +70 °C
TA = –40 to +85 °C
When DPLL is
not used
TA = –10 to +70 °C
TA = –40 to +85 °C
ECHO BACK mode
Without SDLC Loop delay
TX INT mode
TX DMA mode
RX INT mode
RX DMA mode
Note Of STRXC and TRXC, the one used as the receive clock.
Rated Value
Unit
MIN. MAX.
5
tCYK
125
DC
ns
140
DC
ns
50
DC
ns
55
DC
ns
60
DC
ns
65
DC
ns
140
ns
145
ns
300
ns
305
ns
0
100
ns
0
ns
5
ns
140
ns
145
ns
100
ns
100
ns
4
6
tCYK
4
6
tCYK
7
11
tCYK
7
11
tCYK
140
ns
140
ns
22
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